1. Field of the Invention
The present invention relates to a memory embedded logic LSI device. In particular, the present invention relates to a semiconductor integrated circuit device in which a test is carried out with respect to memory and logic circuits.
2. Description of the Related Art
Conventionally, logic LSI and memory LSI have been used separately from each other as the need arises. However, the semiconductor micro-fabrication technique has recently advanced, and thereby, both logic LSI and memory LSI are assembled into one chip. In recent years, product development has been frequently made in memory embedded logic LSI devices embedding logic and memory circuits in one chip. For example, in DRAM embedded logic LSI devices, DRAMs having memories of several to tens of megabytes have been realized.
Memory circuits have large capacities, and thereby, it is impossible to request chips having no defect at all. In this case, it is common in memory embedded LSI devices to include a redundancy function for repairing fail cells. This redundancy function thereby stabilizes the yield.
FIG. 1 shows the general test flow in the wafer state of embedded LSI memory devices having a redundancy function.
First, a wafer test (first) using a memory tester is carried out. Here, pass/fail determination of memory circuits is not carried out. In this case, since the redundancy function is given, it is determined whether or not an LSI chip is usable as a good chip if defect cell is replaced with a spare cell. If the chip is usable as a good chip after repair using the redundancy function, an address for the replacement is acquired.
In the next repair process, fuse blow is carried out using the address acquired in the wafer test (first).
A wafer test (second) using the memory tester is carried out. This is a test for confirming whether the cell has been correctly replaced with the spare cell.
Finally, a logic test, that is, wafer test (third) using a logic tester is carried out.
The chip passing all of three wafer tests described above is used as good chip.
The memory test shown in FIG. 1 is carried out using a multiplexer separation method calling a direct access method, in general. According to the multiplexer separation method, a memory is tested in a state that the memory circuit is separated from the peripheral logic circuits.
FIG. 2 is a block diagram schematically showing the configuration of a memory embedded logic LSI device employing the multiplexer separation method. The system logic 51 and embedded memory (e.g., RAM) 52 are separated using two multiplexers (MUX) 53 and 54. In other words, the changeover of two multiplexers 53 and 54 is made to guide input and output signals of the memory 52 to a terminal (external terminal). By doing so, input and output terminals of the memory 52 are directly controlled so that the memory test can be carried out.
More specifically, the LSI device entries in a test mode using a test mode (TM) pin. The test mode signal is supplied to multiplexers 53 and 54. Thereafter, system logic 51 and memory 52 commonly using input and output terminals are separated via these multiplexers 53 and 54.
Using the foregoing multiplexer separation method and the memory test, the fail address to be repaired using the redundancy function must be found (called “find repair solution”). The memory tester has a function of storing an address corresponding to a fail memory cell. The fail address is read, and thereafter, the fail memory cell is replaced with a spare cell, and thereby, it can be seen whether or not full bit operation is made.
On the other hand, in memory embedded LSI devices having no redundancy function, the memory test is carried out using a memory BIST (Built-In Self Test) circuit.
FIG. 3 is a block diagram showing the configuration of a conventional memory embedded LSI device including a BIST circuit. A BIST logic controller 61 is a module for controlling a BIST test. An address generator 62 comprises a counter circuit for generating address data supplied to memory. The generated address data is supplied to an address terminal of the memory. In this case, two RAMs (Macro) 63 and 64 are used as the memory. An address control logic 66 determines whether a test is carried out with respect to which of memories (RAM) in the case where several memories such as RAMs 63 and 64 exist. Further, the address control logic 66 controls the wide multiplexer 67, signature register (data compressor) 68, RAMs 63 and 64.
The wide multiplexer 67 selects the output of a test target memory, and supplies it to the signature register 68. The signature register 68 is a parallel data input linear feedback shift register, and compresses the output data of the memory. The tester compares a signal (shift out) outputted from the signature register 68 with an expected value, and thereby, it is determined whether or not a defect occurs in the memory.
Conventionally, the test is carried out for memory embedded logic LSI devices having the redundancy function. In this case, the test cost remarkably increases as compared with logic LSI devices embedding no memory or memory embedded logic LSI devices having no redundancy function. In other words, only the wafer test (third) of FIG. 1 is carried out in the logic LSI devices. On the contrary, three wafer tests must be carried out in the memory embedded logic LSI devices. For this reason, the following problems arise:
(1) Test devices, such as test boards and probe cards for carrying out the test, must be prepared; for this reason, the test cost increases.
(2) Three test are carried out; for this reason, the test time is much longer as compared with that for logic LSI devices, thus the test cost increases.
(3) Two tests, that is, a wafer test for memory testing and a logic test for logic testing must be performed; for this reason, resources for acquiring the evidence data are required twice.
Incidentally, a semiconductor device having a RAM with a BIST is disclosed in JPN. PAT. APPLN. KOKAI Publication No. 4-208880, for example.